%0 Conference Paper %1 conf/glvlsi/ChenTKHR94 %A Chen, Yulin %A Tsai, Wei Kang %A Kurdahi, Fadi J. %A Her, Tzong-Dar %A Ramachandran, Champaka %B Great Lakes Symposium on VLSI %D 1994 %I IEEE %K dblp %P 88-92 %T A performance driven logic synthesis system using delay estimator. %U http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi1994.html#ChenTKHR94 %@ 0-8186-5610-7

@inproceedings{conf/glvlsi/ChenTKHR94, added-at = {2014-09-29T00:00:00.000+0200}, author = {Chen, Yulin and Tsai, Wei Kang and Kurdahi, Fadi J. and Her, Tzong-Dar and Ramachandran, Champaka}, biburl = {https://www.bibsonomy.org/bibtex/20f7a868435f270c2b32ed72f0d2b4618/dblp}, booktitle = {Great Lakes Symposium on VLSI}, crossref = {conf/glvlsi/1994}, ee = {http://dx.doi.org/10.1109/GLSV.1994.289990}, interhash = {836f1f9fff5f8073e764b1d70be2c023}, intrahash = {0f7a868435f270c2b32ed72f0d2b4618}, isbn = {0-8186-5610-7}, keywords = {dblp}, pages = {88-92}, publisher = {IEEE}, timestamp = {2015-06-18T19:32:33.000+0200}, title = {A performance driven logic synthesis system using delay estimator.}, url = {http://dblp.uni-trier.de/db/conf/glvlsi/glvlsi1994.html#ChenTKHR94}, year = 1994 }