Low-Spur, Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Recirculating DLL With Dual-Pulse Ring Oscillator and Self-Correcting Charge Pump.
S. Gierkink. IEEE J. Solid State Circuits, 43 (12):
2967-2976(2008)
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%0 Journal Article
%1 journals/jssc/Gierkink08a
%A Gierkink, Sander L. J.
%D 2008
%J IEEE J. Solid State Circuits
%K dblp
%N 12
%P 2967-2976
%T Low-Spur, Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Recirculating DLL With Dual-Pulse Ring Oscillator and Self-Correcting Charge Pump.
%U http://dblp.uni-trier.de/db/journals/jssc/jssc43.html#Gierkink08a
%V 43
@article{journals/jssc/Gierkink08a,
added-at = {2020-08-30T00:00:00.000+0200},
author = {Gierkink, Sander L. J.},
biburl = {https://www.bibsonomy.org/bibtex/2a1d3157c471fe78c37226a10649d2bd4/dblp},
ee = {https://doi.org/10.1109/JSSC.2008.2006225},
interhash = {83d0bb4267c5340bdd0c4e9c6d3bc9b4},
intrahash = {a1d3157c471fe78c37226a10649d2bd4},
journal = {IEEE J. Solid State Circuits},
keywords = {dblp},
number = 12,
pages = {2967-2976},
timestamp = {2020-08-31T11:43:15.000+0200},
title = {Low-Spur, Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Recirculating DLL With Dual-Pulse Ring Oscillator and Self-Correcting Charge Pump.},
url = {http://dblp.uni-trier.de/db/journals/jssc/jssc43.html#Gierkink08a},
volume = 43,
year = 2008
}
