%0 Conference Paper %1 conf/vlsid/PengAG02 %A Peng, Junyu %A Abdi, Samar %A Gajski, Daniel %B ASP-DAC/VLSI Design %D 2002 %I IEEE Computer Society %K dblp %P 332-337 %T Automatic Model Refinement for Fast Architecture Exploration. %U http://dblp.uni-trier.de/db/conf/vlsid/vlsid2002.html#PengAG02 %@ 0-7695-1299-2

@inproceedings{conf/vlsid/PengAG02, added-at = {2022-11-14T00:00:00.000+0100}, author = {Peng, Junyu and Abdi, Samar and Gajski, Daniel}, biburl = {https://www.bibsonomy.org/bibtex/25c62541866d00486d6db2693121f4f75/dblp}, booktitle = {ASP-DAC/VLSI Design}, crossref = {conf/vlsid/2002}, ee = {https://dl.acm.org/doi/10.5555/832284.835457}, interhash = {86e87d2277740f40d3fab716f85c59aa}, intrahash = {5c62541866d00486d6db2693121f4f75}, isbn = {0-7695-1299-2}, keywords = {dblp}, pages = {332-337}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T01:05:13.000+0200}, title = {Automatic Model Refinement for Fast Architecture Exploration.}, url = {http://dblp.uni-trier.de/db/conf/vlsid/vlsid2002.html#PengAG02}, year = 2002 }