%0 Conference Paper %1 conf/iscas/HsiaoHL04 %A Hsiao, Pei-Yung %A Hua, Chun-Ho %A Lin, Chien-Chen %B ISCAS (2) %D 2004 %I IEEE %K dblp %P 593-596 %T A novel FPGA architectural implementation of pipelined thinning algorithm. %U http://dblp.uni-trier.de/db/conf/iscas/iscas2004-2.html#HsiaoHL04 %@ 0-7803-8251-X

@inproceedings{conf/iscas/HsiaoHL04, added-at = {2016-05-20T00:00:00.000+0200}, author = {Hsiao, Pei-Yung and Hua, Chun-Ho and Lin, Chien-Chen}, biburl = {https://www.bibsonomy.org/bibtex/2d4519bc2a0bb681f106e82b04ea4b881/dblp}, booktitle = {ISCAS (2)}, crossref = {conf/iscas/2004}, ee = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9255}, interhash = {8737eca095978b3bcbb34774aa27888d}, intrahash = {d4519bc2a0bb681f106e82b04ea4b881}, isbn = {0-7803-8251-X}, keywords = {dblp}, pages = {593-596}, publisher = {IEEE}, timestamp = {2016-05-21T12:25:01.000+0200}, title = {A novel FPGA architectural implementation of pipelined thinning algorithm.}, url = {http://dblp.uni-trier.de/db/conf/iscas/iscas2004-2.html#HsiaoHL04}, year = 2004 }