%0 Conference Paper %1 conf/ccece/RezkW06 %A Rezk, Dherar %A Wang, Xiaofeng %B CCECE %D 2006 %I IEEE %K dblp %P 932-935 %T Improved Layered Space Time Architecture Through Unequal Power Allocation and Multistage Decoding. %U http://dblp.uni-trier.de/db/conf/ccece/ccece2006.html#RezkW06 %@ 1-4244-0038-4

@inproceedings{conf/ccece/RezkW06, added-at = {2018-08-09T00:00:00.000+0200}, author = {Rezk, Dherar and Wang, Xiaofeng}, biburl = {https://www.bibsonomy.org/bibtex/2e7245012fc977e7e0f00a3e26e7a3c7c/dblp}, booktitle = {CCECE}, crossref = {conf/ccece/2006}, ee = {https://doi.org/10.1109/CCECE.2006.277331}, interhash = {8a8febeef22f8254668d410348080cd5}, intrahash = {e7245012fc977e7e0f00a3e26e7a3c7c}, isbn = {1-4244-0038-4}, keywords = {dblp}, pages = {932-935}, publisher = {IEEE}, timestamp = {2018-08-10T11:38:17.000+0200}, title = {Improved Layered Space Time Architecture Through Unequal Power Allocation and Multistage Decoding.}, url = {http://dblp.uni-trier.de/db/conf/ccece/ccece2006.html#RezkW06}, year = 2006 }