DESIGN AND PERFORMANCE COMPARISON OF AVERAGE 8T SRAM WITH EXISTING 8T SRAM CELLS
International Journal on Recent and Innovation Trends in Computing and Communication, 3 (2):
856--860 (February 2015)DOI: 10.17762/ijritcc2321-8169.150293
Abstract
This paper presents 8T SRAM cell by using various techniques. The conflicting design requirement of read versus write operation in a conventional 8T SRAM bit cell is eliminated using separate read/write access transistors The read stability and the write-ability can be optimized independently by optimizing the respective access transistor size. A new average-8T write/read decoupled SRAM architecture for low-power sub/near-threshold SRAM used in power-constraint applications such as biomedical implants and autonomous sensor nodes. The proposed architecture consists of several novel concepts in dealing with issues in sub/near-threshold SRAM including the differential and data-independent-leakage read port that facilitates robust and faster read operation Simulation result of 8T SRAM design using TANNER tool shows the reduction in total average power and delay