%0 Conference Paper %1 conf/hpec/WijeratneKP21 %A Wijeratne, Sasindu %A Kannan, Rajgopal %A Prasanna, Viktor K. %B HPEC %D 2021 %I IEEE %K dblp %P 1-7 %T Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA. %U http://dblp.uni-trier.de/db/conf/hpec/hpec2021.html#WijeratneKP21 %@ 978-1-6654-2369-4

@inproceedings{conf/hpec/WijeratneKP21, added-at = {2021-12-06T00:00:00.000+0100}, author = {Wijeratne, Sasindu and Kannan, Rajgopal and Prasanna, Viktor K.}, biburl = {https://www.bibsonomy.org/bibtex/253a063a634802c36c9c644762d684e73/dblp}, booktitle = {HPEC}, crossref = {conf/hpec/2021}, ee = {https://doi.org/10.1109/HPEC49654.2021.9622851}, interhash = {8ccc2c743fe82cd45c1b0bbcfab99d32}, intrahash = {53a063a634802c36c9c644762d684e73}, isbn = {978-1-6654-2369-4}, keywords = {dblp}, pages = {1-7}, publisher = {IEEE}, timestamp = {2024-04-10T01:27:15.000+0200}, title = {Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA.}, url = {http://dblp.uni-trier.de/db/conf/hpec/hpec2021.html#WijeratneKP21}, year = 2021 }