%0 Conference Paper %1 conf/slip/JevticCP09 %A Jevtic, Ruzica %A Carreras, Carlos %A Pejovic, Vukasin %B SLIP %D 2009 %E Cheng, Chung-Kuan %E Reda, Sherief %I ACM %K dblp %P 53-60 %T Floorplan-based FPGA interconnect power estimation in DSP circuits. %U http://dblp.uni-trier.de/db/conf/slip/slip2009.html#JevticCP09 %@ 978-1-60558-576-5

@inproceedings{conf/slip/JevticCP09, added-at = {2023-06-26T00:00:00.000+0200}, author = {Jevtic, Ruzica and Carreras, Carlos and Pejovic, Vukasin}, biburl = {https://www.bibsonomy.org/bibtex/25e71c1aa26408b15bfaaffc38d4b3ef9/dblp}, booktitle = {SLIP}, crossref = {conf/slip/2009}, editor = {Cheng, Chung-Kuan and Reda, Sherief}, ee = {https://doi.org/10.1145/1572471.1572481}, interhash = {8cf1f698700aa0c2f712676006ce8518}, intrahash = {5e71c1aa26408b15bfaaffc38d4b3ef9}, isbn = {978-1-60558-576-5}, keywords = {dblp}, pages = {53-60}, publisher = {ACM}, timestamp = {2024-04-10T06:25:02.000+0200}, title = {Floorplan-based FPGA interconnect power estimation in DSP circuits.}, url = {http://dblp.uni-trier.de/db/conf/slip/slip2009.html#JevticCP09}, year = 2009 }