%0 Conference Paper %1 conf/dac/RajaVBG08 %A Raja, Shiva %A Varadi, F. %A Becer, Murat R. %A Geada, Joao %B DAC %D 2008 %E Fix, Limor %I ACM %K dblp %P 456-461 %T Transistor level gate modeling for accurate and fast timing, noise, and power analysis. %U http://dblp.uni-trier.de/db/conf/dac/dac2008.html#RajaVBG08 %@ 978-1-60558-115-6

@inproceedings{conf/dac/RajaVBG08, added-at = {2024-07-30T00:00:00.000+0200}, author = {Raja, Shiva and Varadi, F. and Becer, Murat R. and Geada, Joao}, biburl = {https://www.bibsonomy.org/bibtex/2c4d87e7d15d142339188f1443fbcf066/dblp}, booktitle = {DAC}, crossref = {conf/dac/2008}, editor = {Fix, Limor}, ee = {https://doi.org/10.1145/1391469.1391588}, interhash = {8dd0089149de483b0757cc1814a21394}, intrahash = {c4d87e7d15d142339188f1443fbcf066}, isbn = {978-1-60558-115-6}, keywords = {dblp}, pages = {456-461}, publisher = {ACM}, timestamp = {2024-08-05T07:37:19.000+0200}, title = {Transistor level gate modeling for accurate and fast timing, noise, and power analysis.}, url = {http://dblp.uni-trier.de/db/conf/dac/dac2008.html#RajaVBG08}, year = 2008 }