%0 Journal Article %1 journals/vlsisp/BeniniVBM97 %A Benini, Luca %A Vuillod, Patrick %A Bogliolo, Alessandro %A Micheli, Giovanni De %D 1997 %J VLSI Signal Processing %K dblp %N 2-3 %P 117-130 %T Clock Skew Optimization for Peak Current Reduction. %U http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp16.html#BeniniVBM97 %V 16

@article{journals/vlsisp/BeniniVBM97, added-at = {2008-08-07T00:00:00.000+0200}, author = {Benini, Luca and Vuillod, Patrick and Bogliolo, Alessandro and Micheli, Giovanni De}, biburl = {https://www.bibsonomy.org/bibtex/22e15e32a24f13296545b6db771becc75/dblp}, date = {2008-08-07}, description = {dblp}, ee = {http://dx.doi.org/10.1023/A:1007982806152}, interhash = {8e9b3ff6049fc5fb8f42f426db06f584}, intrahash = {2e15e32a24f13296545b6db771becc75}, journal = {VLSI Signal Processing}, keywords = {dblp}, number = {2-3}, pages = {117-130}, timestamp = {2008-08-08T11:54:25.000+0200}, title = {Clock Skew Optimization for Peak Current Reduction.}, url = {http://dblp.uni-trier.de/db/journals/vlsisp/vlsisp16.html#BeniniVBM97}, volume = 16, year = 1997 }