%0 Journal Article %1 journals/tcad/KrestinskayaIJ18 %A Krestinskaya, Olga %A Ibrayev, Timur %A James, Alex Pappachen %D 2018 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 6 %P 1143-1156 %T Hierarchical Temporal Memory Features with Memristor Logic Circuits for Pattern Recognition. %U http://dblp.uni-trier.de/db/journals/tcad/tcad37.html#KrestinskayaIJ18 %V 37

@article{journals/tcad/KrestinskayaIJ18, added-at = {2022-06-23T00:00:00.000+0200}, author = {Krestinskaya, Olga and Ibrayev, Timur and James, Alex Pappachen}, biburl = {https://www.bibsonomy.org/bibtex/2e779fc2b398606308828e22a9341dede/dblp}, ee = {https://doi.org/10.1109/TCAD.2017.2748024}, interhash = {939d28e2cc59f7c112bfb3735db0012e}, intrahash = {e779fc2b398606308828e22a9341dede}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 6, pages = {1143-1156}, timestamp = {2024-04-08T19:46:25.000+0200}, title = {Hierarchical Temporal Memory Features with Memristor Logic Circuits for Pattern Recognition.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad37.html#KrestinskayaIJ18}, volume = 37, year = 2018 }