%0 Journal Article %1 journals/integration/TiwariAM96 %A Tiwari, Vivek %A Ashar, Pranav %A Malik, Sharad %D 1996 %J Integr. %K dblp %N 3 %P 243-268 %T Technology mapping for low power in logic synthesis. %U http://dblp.uni-trier.de/db/journals/integration/integration20.html#TiwariAM96 %V 20

@article{journals/integration/TiwariAM96, added-at = {2023-09-30T00:00:00.000+0200}, author = {Tiwari, Vivek and Ashar, Pranav and Malik, Sharad}, biburl = {https://www.bibsonomy.org/bibtex/20edaf476ddc051f09203b6ea5daf4d21/dblp}, ee = {https://doi.org/10.1016/0167-9260(96)00002-8}, interhash = {9470757910a8c595601d9e9830471a9d}, intrahash = {0edaf476ddc051f09203b6ea5daf4d21}, journal = {Integr.}, keywords = {dblp}, number = 3, pages = {243-268}, timestamp = {2024-04-08T13:15:16.000+0200}, title = {Technology mapping for low power in logic synthesis.}, url = {http://dblp.uni-trier.de/db/journals/integration/integration20.html#TiwariAM96}, volume = 20, year = 1996 }