%0 Conference Paper %1 conf/nanoarch/ChevillonML12 %A Chevillon, Nicolas %A Madec, Morgan %A Lallement, Christophe %B NANOARCH %D 2012 %E Moritz, Csaba Andras %I ACM %K dblp %P 22-29 %T Gate-level modeling for CMOS circuit simulation with ultimate FinFETs. %U http://dblp.uni-trier.de/db/conf/nanoarch/nanoarch2012.html#ChevillonML12 %@ 978-1-4503-1671-2

@inproceedings{conf/nanoarch/ChevillonML12, added-at = {2021-08-11T00:00:00.000+0200}, author = {Chevillon, Nicolas and Madec, Morgan and Lallement, Christophe}, biburl = {https://www.bibsonomy.org/bibtex/23695f43f18b25dca7525acfb8bbb581a/dblp}, booktitle = {NANOARCH}, crossref = {conf/nanoarch/2012}, editor = {Moritz, Csaba Andras}, ee = {https://ieeexplore.ieee.org/document/6464139/}, interhash = {99251fa18299794b2a5e15a2ade7ff38}, intrahash = {3695f43f18b25dca7525acfb8bbb581a}, isbn = {978-1-4503-1671-2}, keywords = {dblp}, pages = {22-29}, publisher = {ACM}, timestamp = {2024-04-10T18:04:15.000+0200}, title = {Gate-level modeling for CMOS circuit simulation with ultimate FinFETs.}, url = {http://dblp.uni-trier.de/db/conf/nanoarch/nanoarch2012.html#ChevillonML12}, year = 2012 }