%0 Journal Article %1 journals/access/DingMGZ18 %A Ding, Ran %A Mei, Jun %A Guan, Zhou %A Zhao, Jianfeng %D 2018 %J IEEE Access %K dblp %P 75961-75974 %T An Input-Series-Output-Series Modular Multilevel DC Transformer With Inter-Module Arithmetic Phase Interleaving Control to Reduce DC Ripples. %U http://dblp.uni-trier.de/db/journals/access/access6.html#DingMGZ18 %V 6

@article{journals/access/DingMGZ18, added-at = {2021-03-08T00:00:00.000+0100}, author = {Ding, Ran and Mei, Jun and Guan, Zhou and Zhao, Jianfeng}, biburl = {https://www.bibsonomy.org/bibtex/2c66f5b02a41130542809eaed5ec1fbd8/dblp}, ee = {https://doi.org/10.1109/ACCESS.2018.2882807}, interhash = {9d34557ff2b7216e8b64b9aee7d76e7a}, intrahash = {c66f5b02a41130542809eaed5ec1fbd8}, journal = {IEEE Access}, keywords = {dblp}, pages = {75961-75974}, timestamp = {2024-04-08T14:11:30.000+0200}, title = {An Input-Series-Output-Series Modular Multilevel DC Transformer With Inter-Module Arithmetic Phase Interleaving Control to Reduce DC Ripples.}, url = {http://dblp.uni-trier.de/db/journals/access/access6.html#DingMGZ18}, volume = 6, year = 2018 }