%0 Conference Paper %1 conf/vlsit/JungmannJKSHCML23 %A Jungmann, N. %A Joshi, R. %A Kachir, E. %A Shimanovich, K. %A He, B. %A Cohen, T. %A Miller, T. %A Leu, D. %A Kannambadi, Dinesh %A Wagner, I. %A Reyer, Kenneth %A Konen, H. %A Suleiman, M. %A Sindhe, V. %A Freiman, Y. %B VLSI Technology and Circuits %D 2023 %I IEEE %K dblp %P 1-2 %T A 1.9GHz 0.57V Vmin 576Kb embedded product-ready L2 cache in 5nm FinFET technology. %U http://dblp.uni-trier.de/db/conf/vlsit/vlsit2023.html#JungmannJKSHCML23 %@ 978-4-86348-806-9

@inproceedings{conf/vlsit/JungmannJKSHCML23, added-at = {2023-07-28T00:00:00.000+0200}, author = {Jungmann, N. and Joshi, R. and Kachir, E. and Shimanovich, K. and He, B. and Cohen, T. and Miller, T. and Leu, D. and Kannambadi, Dinesh and Wagner, I. and Reyer, Kenneth and Konen, H. and Suleiman, M. and Sindhe, V. and Freiman, Y.}, biburl = {https://www.bibsonomy.org/bibtex/2037bd7e5d1278191b8f2b565615e07b1/dblp}, booktitle = {VLSI Technology and Circuits}, crossref = {conf/vlsit/2023}, ee = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185232}, interhash = {9e1728e19f9be195d837e2cd4794735c}, intrahash = {037bd7e5d1278191b8f2b565615e07b1}, isbn = {978-4-86348-806-9}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2024-04-09T19:13:01.000+0200}, title = {A 1.9GHz 0.57V Vmin 576Kb embedded product-ready L2 cache in 5nm FinFET technology.}, url = {http://dblp.uni-trier.de/db/conf/vlsit/vlsit2023.html#JungmannJKSHCML23}, year = 2023 }