%0 Journal Article %1 journals/tcas/Chang08 %A Chang, Yun-Nan %D 2008 %J IEEE Trans. Circuits Syst. II Express Briefs %K dblp %N 12 %P 1234-1238 %T An Efficient VLSI Architecture for Normal I/O Order Pipeline FFT Design. %U http://dblp.uni-trier.de/db/journals/tcas/tcasII55.html#Chang08 %V 55-II

@article{journals/tcas/Chang08, added-at = {2020-05-27T00:00:00.000+0200}, author = {Chang, Yun-Nan}, biburl = {https://www.bibsonomy.org/bibtex/2a24d3c5c3f1b9f23def0a8ad3f6eb50c/dblp}, ee = {https://doi.org/10.1109/TCSII.2008.2008074}, interhash = {a05be6bf169c2f0feb5ba0f9a6e018dd}, intrahash = {a24d3c5c3f1b9f23def0a8ad3f6eb50c}, journal = {IEEE Trans. Circuits Syst. II Express Briefs}, keywords = {dblp}, number = 12, pages = {1234-1238}, timestamp = {2020-05-28T11:53:24.000+0200}, title = {An Efficient VLSI Architecture for Normal I/O Order Pipeline FFT Design.}, url = {http://dblp.uni-trier.de/db/journals/tcas/tcasII55.html#Chang08}, volume = {55-II}, year = 2008 }