%0 Conference Paper %1 conf/asicon/RaoWWW13 %A Rao, Xiantuo %A Wang, Teng %A Wang, Xin'an %A Wang, Yinhui %B ASICON %D 2013 %I IEEE %K dblp %P 1-4 %T A low-power and high-efficiency cache design for embedded bus-based symmetric multiprocessors. %U http://dblp.uni-trier.de/db/conf/asicon/asicon2013.html#RaoWWW13 %@ 978-1-4673-6415-7

@inproceedings{conf/asicon/RaoWWW13, added-at = {2015-02-23T00:00:00.000+0100}, author = {Rao, Xiantuo and Wang, Teng and Wang, Xin'an and Wang, Yinhui}, biburl = {https://www.bibsonomy.org/bibtex/245154018a6b2a62efc8f9ffdcae5b39f/dblp}, booktitle = {ASICON}, crossref = {conf/asicon/2013}, ee = {http://dx.doi.org/10.1109/ASICON.2013.6811823}, interhash = {a0aeff03bef6dd9687542ba19e8dbbdb}, intrahash = {45154018a6b2a62efc8f9ffdcae5b39f}, isbn = {978-1-4673-6415-7}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2015-06-19T16:17:58.000+0200}, title = {A low-power and high-efficiency cache design for embedded bus-based symmetric multiprocessors.}, url = {http://dblp.uni-trier.de/db/conf/asicon/asicon2013.html#RaoWWW13}, year = 2013 }