%0 Journal Article %1 journals/tcad/PecheuxLV05 %A Pêcheux, François %A Lallement, Christophe %A Vachoux, Alain %D 2005 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 2 %P 204-225 %T VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems. %U http://dblp.uni-trier.de/db/journals/tcad/tcad24.html#PecheuxLV05 %V 24

@article{journals/tcad/PecheuxLV05, added-at = {2020-09-24T00:00:00.000+0200}, author = {Pêcheux, François and Lallement, Christophe and Vachoux, Alain}, biburl = {https://www.bibsonomy.org/bibtex/22bc5e360a7b92eb904722119b734d4a9/dblp}, ee = {https://doi.org/10.1109/TCAD.2004.841071}, interhash = {a1d4bd74bc2ea76c433f1bb80b7462ff}, intrahash = {2bc5e360a7b92eb904722119b734d4a9}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 2, pages = {204-225}, timestamp = {2020-09-25T11:50:48.000+0200}, title = {VHDL-AMS and Verilog-AMS as alternative hardware description languages for efficient modeling of multidiscipline systems.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad24.html#PecheuxLV05}, volume = 24, year = 2005 }