%0 Conference Paper %1 conf/vlsit/TaoZSLH23 %A Tao, Weichen %A Zhao, Weichen %A Staszewski, Robert Bogdan %A Lin, Fujiang %A Hu, Yizhe %B VLSI Technology and Circuits %D 2023 %I IEEE %K dblp %P 1-2 %T An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and -252 dB FoM. %U http://dblp.uni-trier.de/db/conf/vlsit/vlsit2023.html#TaoZSLH23 %@ 978-4-86348-806-9

@inproceedings{conf/vlsit/TaoZSLH23, added-at = {2023-07-28T00:00:00.000+0200}, author = {Tao, Weichen and Zhao, Weichen and Staszewski, Robert Bogdan and Lin, Fujiang and Hu, Yizhe}, biburl = {https://www.bibsonomy.org/bibtex/258e82b3b9f61b3e97cf16391306e6829/dblp}, booktitle = {VLSI Technology and Circuits}, crossref = {conf/vlsit/2023}, ee = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185415}, interhash = {a1f54d78f611c350836ac79880c0662d}, intrahash = {58e82b3b9f61b3e97cf16391306e6829}, isbn = {978-4-86348-806-9}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2024-04-09T19:13:01.000+0200}, title = {An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and -252 dB FoM.}, url = {http://dblp.uni-trier.de/db/conf/vlsit/vlsit2023.html#TaoZSLH23}, year = 2023 }