%0 Conference Paper %1 conf/fpga/CevreroAPBLIS09 %A Cevrero, Alessandro %A Athanasopoulos, Panagiotis %A Parandeh-Afshar, Hadi %A Brisk, Philip %A Leblebici, Yusuf %A Ienne, Paolo %A Skerlj, Maurizio %B FPGA %D 2009 %E Chow, Paul %E Cheung, Peter Y. K. %I ACM %K dblp %P 286 %T 3D configuration caching for 2D FPGAs. %U http://dblp.uni-trier.de/db/conf/fpga/fpga2009.html#CevreroAPBLIS09 %@ 978-1-60558-410-2

@inproceedings{conf/fpga/CevreroAPBLIS09, added-at = {2018-11-06T00:00:00.000+0100}, author = {Cevrero, Alessandro and Athanasopoulos, Panagiotis and Parandeh-Afshar, Hadi and Brisk, Philip and Leblebici, Yusuf and Ienne, Paolo and Skerlj, Maurizio}, biburl = {https://www.bibsonomy.org/bibtex/27e7d0f63d01bc2807eaec950801635a8/dblp}, booktitle = {FPGA}, crossref = {conf/fpga/2009}, editor = {Chow, Paul and Cheung, Peter Y. K.}, ee = {https://doi.org/10.1145/1508128.1508205}, interhash = {a26610988c5b918c6714e5febf597202}, intrahash = {7e7d0f63d01bc2807eaec950801635a8}, isbn = {978-1-60558-410-2}, keywords = {dblp}, pages = 286, publisher = {ACM}, timestamp = {2018-11-07T12:46:52.000+0100}, title = {3D configuration caching for 2D FPGAs.}, url = {http://dblp.uni-trier.de/db/conf/fpga/fpga2009.html#CevreroAPBLIS09}, year = 2009 }