%0 Journal Article %1 journals/cssp/YuanZYMP24 %A Yuan, Jun %A Zhang, Yuyang %A Yuan, Caizheng %A Meng, Xiangsheng %A Pan, Yonghong %D 2024 %J Circuits Syst. Signal Process. %K dblp %N 4 %P 2560-2584 %T FPGA Design and Implementation of Improved DFxLMS Algorithm for Compressor Noise Cancellation System. %U http://dblp.uni-trier.de/db/journals/cssp/cssp43.html#YuanZYMP24 %V 43

@article{journals/cssp/YuanZYMP24, added-at = {2024-03-16T00:00:00.000+0100}, author = {Yuan, Jun and Zhang, Yuyang and Yuan, Caizheng and Meng, Xiangsheng and Pan, Yonghong}, biburl = {https://www.bibsonomy.org/bibtex/2a04cb19acd1756374a18f320b38de257/dblp}, ee = {https://doi.org/10.1007/s00034-023-02577-y}, interhash = {a276754fa019415b1e75870160a6d132}, intrahash = {a04cb19acd1756374a18f320b38de257}, journal = {Circuits Syst. Signal Process.}, keywords = {dblp}, month = {April}, number = 4, pages = {2560-2584}, timestamp = {2024-04-08T15:53:22.000+0200}, title = {FPGA Design and Implementation of Improved DFxLMS Algorithm for Compressor Noise Cancellation System.}, url = {http://dblp.uni-trier.de/db/journals/cssp/cssp43.html#YuanZYMP24}, volume = 43, year = 2024 }