%0 Conference Paper %1 conf/vlsi/LinSK16 %A Lin, Minghao %A Sun, Heming %A Kimura, Shinji %B VLSI-SoC %D 2016 %I IEEE %K dblp %P 1-6 %T Power-efficient and slew-aware three dimensional gated clock tree synthesis. %U http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2016.html#LinSK16 %@ 978-1-5090-3561-8

@inproceedings{conf/vlsi/LinSK16, added-at = {2018-11-30T00:00:00.000+0100}, author = {Lin, Minghao and Sun, Heming and Kimura, Shinji}, biburl = {https://www.bibsonomy.org/bibtex/2c861f13ac02cfeaebf015f2405811f8d/dblp}, booktitle = {VLSI-SoC}, crossref = {conf/vlsi/2016soc}, ee = {https://doi.org/10.1109/VLSI-SoC.2016.7753535}, interhash = {a6a39a784ef8f2592d16baf747f2e9ea}, intrahash = {c861f13ac02cfeaebf015f2405811f8d}, isbn = {978-1-5090-3561-8}, keywords = {dblp}, pages = {1-6}, publisher = {IEEE}, timestamp = {2019-10-17T14:01:58.000+0200}, title = {Power-efficient and slew-aware three dimensional gated clock tree synthesis.}, url = {http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2016.html#LinSK16}, year = 2016 }