%0 Journal Article %1 journals/tcas/WangHR17 %A Wang, Chua-Chin %A Hou, Zong-You %A Ruan, Kai-Wei %D 2017 %J IEEE Trans. Circuits Syst. II Express Briefs %K dblp %N 7 %P 812-816 %T 2×VDD 40-nm CMOS Output Buffer With Slew Rate Self-Adjustment Using Leakage Compensation. %U http://dblp.uni-trier.de/db/journals/tcas/tcasII64.html#WangHR17 %V 64-II

@article{journals/tcas/WangHR17, added-at = {2020-05-27T00:00:00.000+0200}, author = {Wang, Chua-Chin and Hou, Zong-You and Ruan, Kai-Wei}, biburl = {https://www.bibsonomy.org/bibtex/28c247fdc9f1982bc1952d6c2459e7fda/dblp}, ee = {https://doi.org/10.1109/TCSII.2016.2599538}, interhash = {a74ac790873866d92f0ccb6245737aa1}, intrahash = {8c247fdc9f1982bc1952d6c2459e7fda}, journal = {IEEE Trans. Circuits Syst. II Express Briefs}, keywords = {dblp}, number = 7, pages = {812-816}, timestamp = {2020-05-28T11:52:44.000+0200}, title = {2×VDD 40-nm CMOS Output Buffer With Slew Rate Self-Adjustment Using Leakage Compensation.}, url = {http://dblp.uni-trier.de/db/journals/tcas/tcasII64.html#WangHR17}, volume = {64-II}, year = 2017 }