%0 Conference Paper %1 conf/aspdac/TsaiC05 %A Tsai, Jeng-Liang %A Chen, Charlie Chung-Ping %B ASP-DAC %D 2005 %E Tang, Tingao %I ACM Press %K dblp %P 1168-1171 %T Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling. %U http://dblp.uni-trier.de/db/conf/aspdac/aspdac2005.html#TsaiC05 %@ 0-7803-8737-6

@inproceedings{conf/aspdac/TsaiC05, added-at = {2018-11-06T00:00:00.000+0100}, author = {Tsai, Jeng-Liang and Chen, Charlie Chung-Ping}, biburl = {https://www.bibsonomy.org/bibtex/2f7bbe0f88776a4f75984bf0c4cbfa348/dblp}, booktitle = {ASP-DAC}, crossref = {conf/aspdac/2005}, editor = {Tang, Tingao}, ee = {https://doi.org/10.1109/ASPDAC.2005.1466549}, interhash = {a8c57f367daa6a25f809acd209c080db}, intrahash = {f7bbe0f88776a4f75984bf0c4cbfa348}, isbn = {0-7803-8737-6}, keywords = {dblp}, pages = {1168-1171}, publisher = {ACM Press}, timestamp = {2019-10-17T16:43:15.000+0200}, title = {Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling.}, url = {http://dblp.uni-trier.de/db/conf/aspdac/aspdac2005.html#TsaiC05}, year = 2005 }