%0 Conference Paper %1 conf/vlsi/BazeghiMR07 %A Bazeghi, Cyrus %A Mesa-Martinez, Francisco J. %A Renau, Jose %B VLSI-SoC (Selected Papers) %D 2007 %I Springer %K dblp %P 1-21 %T System and Procesor Design Effort Estimation. %U http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2007s.html#BazeghiMR07 %V 291 %@ 978-0-387-93845-5

@inproceedings{conf/vlsi/BazeghiMR07, added-at = {2018-06-26T00:00:00.000+0200}, author = {Bazeghi, Cyrus and Mesa-Martinez, Francisco J. and Renau, Jose}, biburl = {https://www.bibsonomy.org/bibtex/26193bc015665c138f3e772a6aee4c812/dblp}, booktitle = {VLSI-SoC (Selected Papers)}, crossref = {conf/vlsi/2007socs}, ee = {https://doi.org/10.1007/978-0-387-89558-1_14}, interhash = {aa9ee4d1c771b4f17438a457ad0b6f4f}, intrahash = {6193bc015665c138f3e772a6aee4c812}, isbn = {978-0-387-93845-5}, keywords = {dblp}, pages = {1-21}, publisher = {Springer}, series = {IFIP}, timestamp = {2018-06-27T12:48:23.000+0200}, title = {System and Procesor Design Effort Estimation.}, url = {http://dblp.uni-trier.de/db/conf/vlsi/vlsisoc2007s.html#BazeghiMR07}, volume = 291, year = 2007 }