%0 Conference Paper %1 conf/ismvl/HaradaBKF14 %A Harada, Shintaro %A Bai, Xu %A Kameyama, Michitaka %A Fujioka, Yoshichika %B ISMVL %D 2014 %I IEEE Computer Society %K dblp %P 214-219 %T Design of a Logic-in-Memory Multiple-Valued Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme. %U http://dblp.uni-trier.de/db/conf/ismvl/ismvl2014.html#HaradaBKF14 %@ 978-1-4799-3534-5

@inproceedings{conf/ismvl/HaradaBKF14, added-at = {2023-03-23T00:00:00.000+0100}, author = {Harada, Shintaro and Bai, Xu and Kameyama, Michitaka and Fujioka, Yoshichika}, biburl = {https://www.bibsonomy.org/bibtex/228b82b3eb93ecbcf7864fb727e8b8a0a/dblp}, booktitle = {ISMVL}, crossref = {conf/ismvl/2014}, ee = {https://doi.ieeecomputersociety.org/10.1109/ISMVL.2014.45}, interhash = {aaf696a746b0aa754631325304c90d90}, intrahash = {28b82b3eb93ecbcf7864fb727e8b8a0a}, isbn = {978-1-4799-3534-5}, keywords = {dblp}, pages = {214-219}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T17:17:02.000+0200}, title = {Design of a Logic-in-Memory Multiple-Valued Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme.}, url = {http://dblp.uni-trier.de/db/conf/ismvl/ismvl2014.html#HaradaBKF14}, year = 2014 }