%0 Journal Article %1 journals/iet-cdt/LiuQ17 %A Liu, Qiang %A Qian, HanJing %D 2017 %J IET Comput. Digit. Tech. %K dblp %N 3 %P 117-123 %T Fast and accurate circuit delay model for FPGA architectural exploration. %U http://dblp.uni-trier.de/db/journals/iet-cdt/iet-cdt11.html#LiuQ17 %V 11

@article{journals/iet-cdt/LiuQ17, added-at = {2020-07-14T00:00:00.000+0200}, author = {Liu, Qiang and Qian, HanJing}, biburl = {https://www.bibsonomy.org/bibtex/24ac32c4c60f791578f6948d4e1864f1f/dblp}, ee = {https://doi.org/10.1049/iet-cdt.2016.0053}, interhash = {ae6a7b4fcdcae26a58b93ce394cf0f45}, intrahash = {4ac32c4c60f791578f6948d4e1864f1f}, journal = {IET Comput. Digit. Tech.}, keywords = {dblp}, number = 3, pages = {117-123}, timestamp = {2020-07-24T00:16:18.000+0200}, title = {Fast and accurate circuit delay model for FPGA architectural exploration.}, url = {http://dblp.uni-trier.de/db/journals/iet-cdt/iet-cdt11.html#LiuQ17}, volume = 11, year = 2017 }