Bitte melden Sie sich an um selbst Rezensionen oder Kommentare zu erstellen.
Zitieren Sie diese Publikation
Mehr Zitationsstile
- bitte auswählen -
%0 Conference Paper
%1 conf/fpl/PistoriusHSIJT07
%A Pistorius, Joachim
%A Hutton, Mike
%A Schleicher, Jay
%A Iotov, Mihail
%A Julias, Enoch
%A Tharmalingam, Kumara
%B FPL
%D 2007
%E Bertels, Koen
%E Najjar, Walid A.
%E van Genderen, Arjan J.
%E Vassiliadis, Stamatis
%I IEEE
%K dblp
%P 423-428
%T Equivalence Verification of FPGA and Structured ASIC Implementations.
%U http://dblp.uni-trier.de/db/conf/fpl/fpl2007.html#PistoriusHSIJT07
%@ 1-4244-1060-6
@inproceedings{conf/fpl/PistoriusHSIJT07,
added-at = {2017-05-21T00:00:00.000+0200},
author = {Pistorius, Joachim and Hutton, Mike and Schleicher, Jay and Iotov, Mihail and Julias, Enoch and Tharmalingam, Kumara},
biburl = {https://www.bibsonomy.org/bibtex/28c44f6d0acbc760353a32cc0c10d4c55/dblp},
booktitle = {FPL},
crossref = {conf/fpl/2007},
editor = {Bertels, Koen and Najjar, Walid A. and van Genderen, Arjan J. and Vassiliadis, Stamatis},
ee = {https://doi.org/10.1109/FPL.2007.4380683},
interhash = {aedc9e83e6bc68a01918fd3fc9592630},
intrahash = {8c44f6d0acbc760353a32cc0c10d4c55},
isbn = {1-4244-1060-6},
keywords = {dblp},
pages = {423-428},
publisher = {IEEE},
timestamp = {2019-10-17T19:13:04.000+0200},
title = {Equivalence Verification of FPGA and Structured ASIC Implementations.},
url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2007.html#PistoriusHSIJT07},
year = 2007
}