%0 Journal Article %1 journals/tcasI/LeePKJ23 %A Lee, Junseo %A Park, Jihwan %A Kim, Seokhun %A Jeong, Hanwool %D 2023 %J IEEE Trans. Circuits Syst. I Regul. Pap. %K dblp %N 12 %P 4949-4961 %T Bayesian Learning Automated SRAM Circuit Design for Power and Performance Optimization. %U http://dblp.uni-trier.de/db/journals/tcasI/tcasI70.html#LeePKJ23 %V 70

@article{journals/tcasI/LeePKJ23, added-at = {2024-01-13T00:00:00.000+0100}, author = {Lee, Junseo and Park, Jihwan and Kim, Seokhun and Jeong, Hanwool}, biburl = {https://www.bibsonomy.org/bibtex/2fc416310b095a7fc1f58f2fc87cc8048/dblp}, ee = {https://doi.org/10.1109/TCSI.2023.3313874}, interhash = {b00ab68872238ea80e27d0306b3406a2}, intrahash = {fc416310b095a7fc1f58f2fc87cc8048}, journal = {IEEE Trans. Circuits Syst. I Regul. Pap.}, keywords = {dblp}, month = {December}, number = 12, pages = {4949-4961}, timestamp = {2024-04-08T16:47:48.000+0200}, title = {Bayesian Learning Automated SRAM Circuit Design for Power and Performance Optimization.}, url = {http://dblp.uni-trier.de/db/journals/tcasI/tcasI70.html#LeePKJ23}, volume = 70, year = 2023 }