%0 Journal Article %1 journals/vlsi/KimC00 %A Kim, Dong-Wook %A Choi, Tae-Yong %D 2000 %J VLSI Design %K dblp %N 2 %P 161-173 %T Delay Time Estimation Model for Large Digital CMOS Circuits. %U http://dblp.uni-trier.de/db/journals/vlsi/vlsi11.html#KimC00 %V 11

@article{journals/vlsi/KimC00, added-at = {2023-05-08T00:00:00.000+0200}, author = {Kim, Dong-Wook and Choi, Tae-Yong}, biburl = {https://www.bibsonomy.org/bibtex/26f454ec0edb4af4eafed3c8b1715cd40/dblp}, ee = {https://doi.org/10.1155/2000/18189}, interhash = {b2b2fede9970d38dea4f1130ecdeb46d}, intrahash = {6f454ec0edb4af4eafed3c8b1715cd40}, journal = {VLSI Design}, keywords = {dblp}, number = 2, pages = {161-173}, timestamp = {2024-04-08T12:07:18.000+0200}, title = {Delay Time Estimation Model for Large Digital CMOS Circuits.}, url = {http://dblp.uni-trier.de/db/journals/vlsi/vlsi11.html#KimC00}, volume = 11, year = 2000 }