%0 Journal Article %1 journals/ieicet/ZhangLWL16 %A Zhang, Yefei %A Li, Zunchao %A Wang, Chuang %A Liang, Feng %D 2016 %J IEICE Trans. Electron. %K dblp %N 2 %P 302-307 %T Compact Analytical Threshold Voltage Model of Strained Gate-All-Around MOSFET Fabricated on Si1-xGex Virtual Substrate. %U http://dblp.uni-trier.de/db/journals/ieicet/ieicet99c.html#ZhangLWL16 %V 99-C

@article{journals/ieicet/ZhangLWL16, added-at = {2020-04-11T00:00:00.000+0200}, author = {Zhang, Yefei and Li, Zunchao and Wang, Chuang and Liang, Feng}, biburl = {https://www.bibsonomy.org/bibtex/2ef9c0b2b6f0431541483d82f8d5601c6/dblp}, ee = {http://search.ieice.org/bin/summary.php?id=e99-c_2_302}, interhash = {b2f8b703c2acffa382dba8755520a2cb}, intrahash = {ef9c0b2b6f0431541483d82f8d5601c6}, journal = {IEICE Trans. Electron.}, keywords = {dblp}, number = 2, pages = {302-307}, timestamp = {2020-04-14T11:50:58.000+0200}, title = {Compact Analytical Threshold Voltage Model of Strained Gate-All-Around MOSFET Fabricated on Si1-xGex Virtual Substrate.}, url = {http://dblp.uni-trier.de/db/journals/ieicet/ieicet99c.html#ZhangLWL16}, volume = {99-C}, year = 2016 }