%0 Conference Paper %1 conf/fpga/HongNL06 %A Hong, Jumnit %A Nurvitadhi, Eriko %A Lu, Shih-Lien %B FPGA %D 2006 %E Wilton, Steven J. E. %E DeHon, André %I ACM %K dblp %P 63-72 %T Design, implementation, and verification of active cache emulator (ACE). %U http://dblp.uni-trier.de/db/conf/fpga/fpga2006.html#HongNL06 %@ 1-59593-292-5

@inproceedings{conf/fpga/HongNL06, added-at = {2018-11-06T00:00:00.000+0100}, author = {Hong, Jumnit and Nurvitadhi, Eriko and Lu, Shih-Lien}, biburl = {https://www.bibsonomy.org/bibtex/21545f6b00c2deb926fd6189a3791f56a/dblp}, booktitle = {FPGA}, crossref = {conf/fpga/2006}, editor = {Wilton, Steven J. E. and DeHon, André}, ee = {https://doi.org/10.1145/1117201.1117211}, interhash = {b3e6a7270635e1327d7131c36fc5cdf6}, intrahash = {1545f6b00c2deb926fd6189a3791f56a}, isbn = {1-59593-292-5}, keywords = {dblp}, pages = {63-72}, publisher = {ACM}, timestamp = {2018-11-07T12:47:21.000+0100}, title = {Design, implementation, and verification of active cache emulator (ACE).}, url = {http://dblp.uni-trier.de/db/conf/fpga/fpga2006.html#HongNL06}, year = 2006 }