%0 Journal Article %1 journals/tcad/PatyalCLFC23 %A Patyal, Abhishek %A Chen, Hung-Ming %A Lin, Mark Po-Hung %A Fang, Guan-Qi %A Chen, Simon Yi-Hung %D 2023 %J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. %K dblp %N 1 %P 266-279 %T Pole-Aware Analog Layout Synthesis Considering Monotonic Current Flows and Wire Crossings. %U http://dblp.uni-trier.de/db/journals/tcad/tcad42.html#PatyalCLFC23 %V 42

@article{journals/tcad/PatyalCLFC23, added-at = {2023-11-12T00:00:00.000+0100}, author = {Patyal, Abhishek and Chen, Hung-Ming and Lin, Mark Po-Hung and Fang, Guan-Qi and Chen, Simon Yi-Hung}, biburl = {https://www.bibsonomy.org/bibtex/2972a430597ebe1a103bc188b57a2afd9/dblp}, ee = {https://www.wikidata.org/entity/Q114147806}, interhash = {b48d6507de2fdc64263dd02def6308b6}, intrahash = {972a430597ebe1a103bc188b57a2afd9}, journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.}, keywords = {dblp}, number = 1, pages = {266-279}, timestamp = {2024-04-08T19:46:10.000+0200}, title = {Pole-Aware Analog Layout Synthesis Considering Monotonic Current Flows and Wire Crossings.}, url = {http://dblp.uni-trier.de/db/journals/tcad/tcad42.html#PatyalCLFC23}, volume = 42, year = 2023 }