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- BibTeX key
- conf/vlsi-dat/HsuWHHLCL17
- entry type
- inproceedings
- booktitle
- VLSI-DAT
- year
- 2017
- pages
- 1-4
- publisher
- IEEE
- crossref
- conf/vlsi-dat/2017
- ee
- https://doi.org/10.1109/VLSI-DAT.2017.7939674
- isbn
- 978-1-5090-3969-2
- url
- http://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2017.html#HsuWHHLCL17
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- please select -%0 Conference Paper
%1 conf/vlsi-dat/HsuWHHLCL17
%A Hsu, Ting-Shuo
%A Wu, Chao-Chieh
%A Hsu, Che-Wei
%A Huang, Chih-Tsun
%A Liou, Jing-Jia
%A Chen, Yao-Hua
%A Lu, Juin-Ming
%B VLSI-DAT
%D 2017
%I IEEE
%K dblp
%P 1-4
%T Design space exploration with a cycle-accurate systemC/TLM DRAM controller model.
%U http://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2017.html#HsuWHHLCL17
%@ 978-1-5090-3969-2
@inproceedings{conf/vlsi-dat/HsuWHHLCL17,
added-at = {2017-06-20T00:00:00.000+0200},
author = {Hsu, Ting-Shuo and Wu, Chao-Chieh and Hsu, Che-Wei and Huang, Chih-Tsun and Liou, Jing-Jia and Chen, Yao-Hua and Lu, Juin-Ming},
biburl = {https://www.bibsonomy.org/bibtex/2bafe27286553dd8b0014ecc8ad829f2d/dblp},
booktitle = {VLSI-DAT},
crossref = {conf/vlsi-dat/2017},
ee = {https://doi.org/10.1109/VLSI-DAT.2017.7939674},
interhash = {b605e0ffce2be7651671294faa9288d7},
intrahash = {bafe27286553dd8b0014ecc8ad829f2d},
isbn = {978-1-5090-3969-2},
keywords = {dblp},
pages = {1-4},
publisher = {IEEE},
timestamp = {2017-06-21T11:38:49.000+0200},
title = {Design space exploration with a cycle-accurate systemC/TLM DRAM controller model.},
url = {http://dblp.uni-trier.de/db/conf/vlsi-dat/vlsi-dat2017.html#HsuWHHLCL17},
year = 2017
}