%0 Conference Paper %1 conf/vlsit/LuLCLCWYCCCCCHL23 %A Lu, C. A. %A Lee, H. P. %A Chen, H. C. %A Lin, Y. C. %A Chung, Y. H. %A Wang, S. H. %A Yeh, J. Y. %A Chang, V. S. %A Chiang, M. C. %A Chang, W. %A Chung, H. C. %A Cheng, C. F. %A Hsu, H. H. %A Liu, H. H. %A Chen, William P. N. %A Lin, C. Y. %B VLSI Technology and Circuits %D 2023 %I IEEE %K dblp %P 1-2 %T Characterizing and Reducing the Layout Dependent Effect and Gate Resistance to Enable Multiple-Vt Scaling for a 3nm CMOS Technology. %U http://dblp.uni-trier.de/db/conf/vlsit/vlsit2023.html#LuLCLCWYCCCCCHL23 %@ 978-4-86348-806-9

@inproceedings{conf/vlsit/LuLCLCWYCCCCCHL23, added-at = {2023-07-28T00:00:00.000+0200}, author = {Lu, C. A. and Lee, H. P. and Chen, H. C. and Lin, Y. C. and Chung, Y. H. and Wang, S. H. and Yeh, J. Y. and Chang, V. S. and Chiang, M. C. and Chang, W. and Chung, H. C. and Cheng, C. F. and Hsu, H. H. and Liu, H. H. and Chen, William P. N. and Lin, C. Y.}, biburl = {https://www.bibsonomy.org/bibtex/2c4564e96c2d53aa63e493ebe27201a32/dblp}, booktitle = {VLSI Technology and Circuits}, crossref = {conf/vlsit/2023}, ee = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185282}, interhash = {b6ca26b6af88853dcf4832162a6e9c9c}, intrahash = {c4564e96c2d53aa63e493ebe27201a32}, isbn = {978-4-86348-806-9}, keywords = {dblp}, pages = {1-2}, publisher = {IEEE}, timestamp = {2024-04-09T19:13:01.000+0200}, title = {Characterizing and Reducing the Layout Dependent Effect and Gate Resistance to Enable Multiple-Vt Scaling for a 3nm CMOS Technology.}, url = {http://dblp.uni-trier.de/db/conf/vlsit/vlsit2023.html#LuLCLCWYCCCCCHL23}, year = 2023 }