%0 Journal Article %1 journals/ieicet/TsaiKL11 %A Tsai, Chia-Chun %A Kuo, Chung-Chieh %A Lee, Trong-Yen %D 2011 %J IEICE Trans. Fundam. Electron. Commun. Comput. Sci. %K dblp %N 2 %P 706-716 %T Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement. %U http://dblp.uni-trier.de/db/journals/ieicet/ieicet94a.html#TsaiKL11 %V 94-A

@article{journals/ieicet/TsaiKL11, added-at = {2020-04-11T00:00:00.000+0200}, author = {Tsai, Chia-Chun and Kuo, Chung-Chieh and Lee, Trong-Yen}, biburl = {https://www.bibsonomy.org/bibtex/2fb29337aeb71b87053fcef71bbded7c6/dblp}, ee = {http://search.ieice.org/bin/summary.php?id=e94-a_2_706}, interhash = {b78e2ca54c955a5e24c0f2d430d55092}, intrahash = {fb29337aeb71b87053fcef71bbded7c6}, journal = {IEICE Trans. Fundam. Electron. Commun. Comput. Sci.}, keywords = {dblp}, number = 2, pages = {706-716}, timestamp = {2020-04-14T11:42:31.000+0200}, title = {Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement.}, url = {http://dblp.uni-trier.de/db/journals/ieicet/ieicet94a.html#TsaiKL11}, volume = {94-A}, year = 2011 }