%0 Journal Article %1 journals/mam/JiLZS17 %A Ji, Kecheng %A Ling, Ming %A Zhang, Yang %A Shi, Longxing %D 2017 %J Microprocess. Microsystems %K dblp %P 66-79 %T An artificial neural network model of LRU-cache misses on out-of-order embedded processors. %U http://dblp.uni-trier.de/db/journals/mam/mam50.html#JiLZS17 %V 50

@article{journals/mam/JiLZS17, added-at = {2020-02-22T00:00:00.000+0100}, author = {Ji, Kecheng and Ling, Ming and Zhang, Yang and Shi, Longxing}, biburl = {https://www.bibsonomy.org/bibtex/265306cdb172233adfb8ffef3df6bce6a/dblp}, ee = {https://doi.org/10.1016/j.micpro.2017.02.005}, interhash = {b8c55beb6b4ed23257c79a2144c233cb}, intrahash = {65306cdb172233adfb8ffef3df6bce6a}, journal = {Microprocess. Microsystems}, keywords = {dblp}, pages = {66-79}, timestamp = {2020-02-25T12:51:02.000+0100}, title = {An artificial neural network model of LRU-cache misses on out-of-order embedded processors.}, url = {http://dblp.uni-trier.de/db/journals/mam/mam50.html#JiLZS17}, volume = 50, year = 2017 }