%0 Conference Paper %1 conf/eitce/LiLWY20 %A Li, Jun %A Liang, Ying %A Wang, Shengkai %A Yang, Jun %B EITCE %D 2020 %I ACM %K dblp %P 658-662 %T Design of Memory Access Module for YOLO v2 Neural Network Accelerator Based on FPGA. %U http://dblp.uni-trier.de/db/conf/eitce/eitce2020.html#LiLWY20 %@ 978-1-4503-8781-1

@inproceedings{conf/eitce/LiLWY20, added-at = {2023-08-04T00:00:00.000+0200}, author = {Li, Jun and Liang, Ying and Wang, Shengkai and Yang, Jun}, biburl = {https://www.bibsonomy.org/bibtex/22f6734c50af10a1c6032c30116cf34d5/dblp}, booktitle = {EITCE}, crossref = {conf/eitce/2020}, ee = {https://doi.org/10.1145/3443467.3443831}, interhash = {b968588e00573ab4e8a434fa15d25258}, intrahash = {2f6734c50af10a1c6032c30116cf34d5}, isbn = {978-1-4503-8781-1}, keywords = {dblp}, pages = {658-662}, publisher = {ACM}, timestamp = {2024-04-10T00:14:18.000+0200}, title = {Design of Memory Access Module for YOLO v2 Neural Network Accelerator Based on FPGA.}, url = {http://dblp.uni-trier.de/db/conf/eitce/eitce2020.html#LiLWY20}, year = 2020 }