%0 Conference Paper %1 conf/asscc/ToyamaYBSO18 %A Toyama, Yosuke %A Yoshioka, Kentaro %A Ban, Koichiro %A Sai, Akihide %A Onizuka, Kohei %B A-SSCC %D 2018 %I IEEE %K dblp %P 1-4 %T A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications. %U http://dblp.uni-trier.de/db/conf/asscc/asscc2018.html#ToyamaYBSO18 %@ 978-1-5386-6413-1

@inproceedings{conf/asscc/ToyamaYBSO18, added-at = {2022-12-07T00:00:00.000+0100}, author = {Toyama, Yosuke and Yoshioka, Kentaro and Ban, Koichiro and Sai, Akihide and Onizuka, Kohei}, biburl = {https://www.bibsonomy.org/bibtex/22609716d47b6c439c863d950f2b2c643/dblp}, booktitle = {A-SSCC}, crossref = {conf/asscc/2018}, ee = {https://doi.org/10.1109/ASSCC.2018.8579253}, interhash = {b998bf9a0a54081c6072f4a47cf7c990}, intrahash = {2609716d47b6c439c863d950f2b2c643}, isbn = {978-1-5386-6413-1}, keywords = {dblp}, pages = {1-4}, publisher = {IEEE}, timestamp = {2024-04-10T21:35:49.000+0200}, title = {A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications.}, url = {http://dblp.uni-trier.de/db/conf/asscc/asscc2018.html#ToyamaYBSO18}, year = 2018 }