Article,
Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module.
J. Warnock, Y. Chan, H. Harrer, S. Carey, G. Salem, D. Malone, R. Puri, J. Zitz, A. Jatkowski, G. Strevig, A. Datta, A. Gattiker, A. Bansal, G. Mayer, Y. Chan, M. Mayo, D. Rude, L. Sigal, T. Strach, H. Smith, H. Wen, P. kin Mak, C. Shum, D. Plass, and C. Webb.IEEE J. Solid State Circuits, 49 (1): 9-18 (2014)
Meta data
- BibTeX key
- journals/jssc/WarnockCHCSMPZJSDGBMCMRSSSWMSPW14
- entry type
- article
- year
- 2014
- journal
- IEEE J. Solid State Circuits
- number
- 1
- pages
- 9-18
- volume
- 49
- ee
- https://doi.org/10.1109/JSSC.2013.2284647
- url
- http://dblp.uni-trier.de/db/journals/jssc/jssc49.html#WarnockCHCSMPZJSDGBMCMRSSSWMSPW14
Tags
Users
Comments and Reviewsshow / hide
Cite this publication
More citation styles
- please select -%0 Journal Article
%1 journals/jssc/WarnockCHCSMPZJSDGBMCMRSSSWMSPW14
%A Warnock, James D.
%A Chan, Yuen H.
%A Harrer, Hubert
%A Carey, Sean M.
%A Salem, Gerard
%A Malone, Doug
%A Puri, Ruchir
%A Zitz, Jeffrey A.
%A Jatkowski, Adam
%A Strevig, Gerald
%A Datta, Ayan
%A Gattiker, Anne
%A Bansal, Aditya
%A Mayer, Guenter
%A Chan, Yiu-Hing
%A Mayo, Mark D.
%A Rude, David L.
%A Sigal, Leon J.
%A Strach, Thomas
%A Smith, Howard H.
%A Wen, Huajun
%A kin Mak, Pak
%A Shum, Chung-Lung Kevin
%A Plass, Donald W.
%A Webb, Charles F.
%D 2014
%J IEEE J. Solid State Circuits
%K dblp
%N 1
%P 9-18
%T Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module.
%U http://dblp.uni-trier.de/db/journals/jssc/jssc49.html#WarnockCHCSMPZJSDGBMCMRSSSWMSPW14
%V 49
@article{journals/jssc/WarnockCHCSMPZJSDGBMCMRSSSWMSPW14,
added-at = {2020-08-30T00:00:00.000+0200},
author = {Warnock, James D. and Chan, Yuen H. and Harrer, Hubert and Carey, Sean M. and Salem, Gerard and Malone, Doug and Puri, Ruchir and Zitz, Jeffrey A. and Jatkowski, Adam and Strevig, Gerald and Datta, Ayan and Gattiker, Anne and Bansal, Aditya and Mayer, Guenter and Chan, Yiu-Hing and Mayo, Mark D. and Rude, David L. and Sigal, Leon J. and Strach, Thomas and Smith, Howard H. and Wen, Huajun and kin Mak, Pak and Shum, Chung-Lung Kevin and Plass, Donald W. and Webb, Charles F.},
biburl = {https://www.bibsonomy.org/bibtex/2d935fb1c33eb48039b95bec6ae92d339/dblp},
ee = {https://doi.org/10.1109/JSSC.2013.2284647},
interhash = {ba0adb1894d50baa671455eab47c593a},
intrahash = {d935fb1c33eb48039b95bec6ae92d339},
journal = {IEEE J. Solid State Circuits},
keywords = {dblp},
number = 1,
pages = {9-18},
timestamp = {2020-08-31T11:44:24.000+0200},
title = {Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module.},
url = {http://dblp.uni-trier.de/db/journals/jssc/jssc49.html#WarnockCHCSMPZJSDGBMCMRSSSWMSPW14},
volume = 49,
year = 2014
}