@inproceedings{conf/isscc/YuanYWLMCTWHZWRXMZ24,
added-at = {2024-03-19T00:00:00.000+0100},
author = {Yuan, Yiyang and Yang, Yiming and Wang, Xinghua and Li, Xiaoran and Ma, Cailian and Chen, Qirui and Tang, Meini and Wei, Xi and Hou, Zhixian and Zhu, Jialiang and Wu, Hao and Ren, Qirui and Xing, Guozhong and Mak, Pui-In and Zhang, Feng},
biburl = {https://www.bibsonomy.org/bibtex/222c66347eb3ed83f936c77528ecb595f/dblp},
booktitle = {ISSCC},
crossref = {conf/isscc/2024},
ee = {https://doi.org/10.1109/ISSCC49657.2024.10454313},
interhash = {be5824b66f06740432b9a35517a273bb},
intrahash = {22c66347eb3ed83f936c77528ecb595f},
isbn = {979-8-3503-0620-0},
keywords = {dblp},
pages = {576-578},
publisher = {IEEE},
timestamp = {2024-04-09T20:43:07.000+0200},
title = {34.6 A 28nm 72.12TFLOPS/W Hybrid-Domain Outer-Product Based Floating-Point SRAM Computing-in-Memory Macro with Logarithm Bit-Width Residual ADC.},
url = {http://dblp.uni-trier.de/db/conf/isscc/isscc2024.html#YuanYWLMCTWHZWRXMZ24},
year = 2024
}