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%0 Journal Article
%1 journals/tvlsi/JingJCZJLL17
%A Jing, Naifeng
%A Jiang, Shunning
%A Chen, Shuang
%A Zhang, Jingjie
%A Jiang, Li
%A Li, Chao
%A Liang, Xiaoyao
%D 2017
%J IEEE Trans. Very Large Scale Integr. Syst.
%K dblp
%N 2
%P 520-533
%T Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU.
%U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi25.html#JingJCZJLL17
%V 25
@article{journals/tvlsi/JingJCZJLL17,
added-at = {2020-07-30T00:00:00.000+0200},
author = {Jing, Naifeng and Jiang, Shunning and Chen, Shuang and Zhang, Jingjie and Jiang, Li and Li, Chao and Liang, Xiaoyao},
biburl = {https://www.bibsonomy.org/bibtex/2aae8c98a5b606a092ac815b141459599/dblp},
ee = {https://doi.org/10.1109/TVLSI.2016.2584623},
interhash = {be7990b491c89c0df6d0e3742da479d5},
intrahash = {aae8c98a5b606a092ac815b141459599},
journal = {IEEE Trans. Very Large Scale Integr. Syst.},
keywords = {dblp},
number = 2,
pages = {520-533},
timestamp = {2020-07-31T11:41:55.000+0200},
title = {Bank Stealing for a Compact and Efficient Register File Architecture in GPGPU.},
url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi25.html#JingJCZJLL17},
volume = 25,
year = 2017
}