%0 Journal Article %1 journals/tvlsi/YangWWLJW20 %A Yang, Peilin %A Wang, Xiao %A Wang, Chengwei %A Li, Fule %A Jiang, Hanjun %A Wang, Zhihua %D 2020 %J IEEE Trans. Very Large Scale Integr. Syst. %K dblp %N 9 %P 2004-2013 %T A 14-bit 200-Ms/s SHA-Less Pipelined ADC With Aperture Error Reduction. %U http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi28.html#YangWWLJW20 %V 28

@article{journals/tvlsi/YangWWLJW20, added-at = {2020-09-19T00:00:00.000+0200}, author = {Yang, Peilin and Wang, Xiao and Wang, Chengwei and Li, Fule and Jiang, Hanjun and Wang, Zhihua}, biburl = {https://www.bibsonomy.org/bibtex/21e558a88dc410afe54944736a0d387e7/dblp}, ee = {https://doi.org/10.1109/TVLSI.2020.3006147}, interhash = {bf3cbdfb89c3ad2655e92404678d1484}, intrahash = {1e558a88dc410afe54944736a0d387e7}, journal = {IEEE Trans. Very Large Scale Integr. Syst.}, keywords = {dblp}, number = 9, pages = {2004-2013}, timestamp = {2020-09-20T11:35:53.000+0200}, title = {A 14-bit 200-Ms/s SHA-Less Pipelined ADC With Aperture Error Reduction.}, url = {http://dblp.uni-trier.de/db/journals/tvlsi/tvlsi28.html#YangWWLJW20}, volume = 28, year = 2020 }