%0 Journal Article %1 journals/jssc/YuSJPSB20 %A Yu, Changzhi %A Sa, Euije %A Jin, Soowan %A Park, Himchan %A Shin, Jongshin %A Burm, Jinwook %D 2020 %J IEEE J. Solid State Circuits %K dblp %N 10 %P 2831-2841 %T A 6.5-12.5-Gb/s Half-Rate Single-Loop All-Digital Referenceless CDR in 28-nm CMOS. %U http://dblp.uni-trier.de/db/journals/jssc/jssc55.html#YuSJPSB20 %V 55

@article{journals/jssc/YuSJPSB20, added-at = {2020-10-06T00:00:00.000+0200}, author = {Yu, Changzhi and Sa, Euije and Jin, Soowan and Park, Himchan and Shin, Jongshin and Burm, Jinwook}, biburl = {https://www.bibsonomy.org/bibtex/236fd796e00f214807e90828532f34210/dblp}, ee = {https://doi.org/10.1109/JSSC.2020.3005750}, interhash = {c097ad832ce20dc55b9229f013251b68}, intrahash = {36fd796e00f214807e90828532f34210}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 10, pages = {2831-2841}, timestamp = {2020-10-07T11:34:08.000+0200}, title = {A 6.5-12.5-Gb/s Half-Rate Single-Loop All-Digital Referenceless CDR in 28-nm CMOS.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc55.html#YuSJPSB20}, volume = 55, year = 2020 }