%0 Conference Paper %1 conf/vts/El-MalehA02 %A El-Maleh, Aiman %A Al-Suwaiyan, Ali %B VTS %D 2002 %I IEEE Computer Society %K dblp %P 53-59 %T An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits. %U http://dblp.uni-trier.de/db/conf/vts/vts2002.html#El-MalehA02 %@ 0-7695-1570-3

@inproceedings{conf/vts/El-MalehA02, added-at = {2023-03-24T00:00:00.000+0100}, author = {El-Maleh, Aiman and Al-Suwaiyan, Ali}, biburl = {https://www.bibsonomy.org/bibtex/2d5a6b89fd4dd9fd28aa157023267c06f/dblp}, booktitle = {VTS}, crossref = {conf/vts/2002}, ee = {https://doi.ieeecomputersociety.org/10.1109/VTS.2002.1011111}, interhash = {c12c676ee92e8850a96c7705c7a18000}, intrahash = {d5a6b89fd4dd9fd28aa157023267c06f}, isbn = {0-7695-1570-3}, keywords = {dblp}, pages = {53-59}, publisher = {IEEE Computer Society}, timestamp = {2024-04-10T19:45:28.000+0200}, title = {An Efficient Test Relaxation Technique for Combinational & Full-Scan Sequential Circuits.}, url = {http://dblp.uni-trier.de/db/conf/vts/vts2002.html#El-MalehA02}, year = 2002 }