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%0 Journal Article
%1 journals/tcad/DekkerBT90
%A Dekker, Rob
%A Beenker, Frans P. M.
%A Thijssen, Loek
%D 1990
%J IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
%K dblp
%N 6
%P 567-572
%T A realistic fault model and test algorithms for static random access memories.
%U http://dblp.uni-trier.de/db/journals/tcad/tcad9.html#DekkerBT90
%V 9
@article{journals/tcad/DekkerBT90,
added-at = {2020-09-24T00:00:00.000+0200},
author = {Dekker, Rob and Beenker, Frans P. M. and Thijssen, Loek},
biburl = {https://www.bibsonomy.org/bibtex/2378827b5290b3b36a5a7300e8e4ee34e/dblp},
ee = {https://doi.org/10.1109/43.55188},
interhash = {c203072b9cb7ff23f977bdebc5d12810},
intrahash = {378827b5290b3b36a5a7300e8e4ee34e},
journal = {IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.},
keywords = {dblp},
number = 6,
pages = {567-572},
timestamp = {2020-09-25T11:45:35.000+0200},
title = {A realistic fault model and test algorithms for static random access memories.},
url = {http://dblp.uni-trier.de/db/journals/tcad/tcad9.html#DekkerBT90},
volume = 9,
year = 1990
}