%0 Conference Paper %1 conf/apccas/LinSWK08 %A Lin, Su-Hon %A Sheu, Ming-Hwa %A Wang, Chao-Hsiang %A Kuo, Yuan-Ching %B APCCAS %D 2008 %I IEEE %K dblp %P 168-171 %T Area-time-power efficient VLSI design for residue-to-binary converter based on moduli set (2n, 2n+1-1, 2n-1). %U http://dblp.uni-trier.de/db/conf/apccas/apccas2008.html#LinSWK08 %@ 978-1-4244-2342-2

@inproceedings{conf/apccas/LinSWK08, added-at = {2014-03-06T00:00:00.000+0100}, author = {Lin, Su-Hon and Sheu, Ming-Hwa and Wang, Chao-Hsiang and Kuo, Yuan-Ching}, biburl = {https://www.bibsonomy.org/bibtex/21efb6cc551f3d392b53064b5b38be076/dblp}, booktitle = {APCCAS}, crossref = {conf/apccas/2008}, ee = {http://dx.doi.org/10.1109/APCCAS.2008.4745987}, interhash = {c208f16df1ba145518155976aafddb52}, intrahash = {1efb6cc551f3d392b53064b5b38be076}, isbn = {978-1-4244-2342-2}, keywords = {dblp}, pages = {168-171}, publisher = {IEEE}, timestamp = {2015-06-19T04:08:13.000+0200}, title = {Area-time-power efficient VLSI design for residue-to-binary converter based on moduli set (2n, 2n+1-1, 2n-1).}, url = {http://dblp.uni-trier.de/db/conf/apccas/apccas2008.html#LinSWK08}, year = 2008 }