%0 Conference Paper %1 conf/isvlsi/FlachRPJR13 %A Flach, Guilherme %A Reimann, Tiago %A Posser, Gracieli %A Johann, Marcelo O. %A Reis, Ricardo %B ISVLSI %D 2013 %I IEEE Computer Socity %K dblp %P 84-89 %T Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities. %U http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2013.html#FlachRPJR13 %@ 978-1-4799-1331-2

@inproceedings{conf/isvlsi/FlachRPJR13, added-at = {2023-03-24T00:00:00.000+0100}, author = {Flach, Guilherme and Reimann, Tiago and Posser, Gracieli and Johann, Marcelo O. and Reis, Ricardo}, biburl = {https://www.bibsonomy.org/bibtex/275fa8396420e0f80f15ea2e0a36221c9/dblp}, booktitle = {ISVLSI}, crossref = {conf/isvlsi/2013}, ee = {https://doi.ieeecomputersociety.org/10.1109/ISVLSI.2013.6654627}, interhash = {c2a4a89450f4bc9bc138a606838563cd}, intrahash = {75fa8396420e0f80f15ea2e0a36221c9}, isbn = {978-1-4799-1331-2}, keywords = {dblp}, pages = {84-89}, publisher = {IEEE Computer Socity}, timestamp = {2024-04-10T11:07:21.000+0200}, title = {Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities.}, url = {http://dblp.uni-trier.de/db/conf/isvlsi/isvlsi2013.html#FlachRPJR13}, year = 2013 }