%0 Journal Article %1 journals/ieicet/TawadaYT13 %A Tawada, Masashi %A Yanagisawa, Masao %A Togawa, Nozomu %D 2013 %J IEICE Trans. Fundam. Electron. Commun. Comput. Sci. %K dblp %N 6 %P 1283-1292 %T A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches. %U http://dblp.uni-trier.de/db/journals/ieicet/ieicet96a.html#TawadaYT13 %V 96-A

@article{journals/ieicet/TawadaYT13, added-at = {2020-10-26T00:00:00.000+0100}, author = {Tawada, Masashi and Yanagisawa, Masao and Togawa, Nozomu}, biburl = {https://www.bibsonomy.org/bibtex/2b601d13791487c3533daa888d709d66b/dblp}, ee = {http://search.ieice.org/bin/summary.php?id=e96-a_6_1283}, interhash = {c31e1d17f649028ee886baf2463d3166}, intrahash = {b601d13791487c3533daa888d709d66b}, journal = {IEICE Trans. Fundam. Electron. Commun. Comput. Sci.}, keywords = {dblp}, number = 6, pages = {1283-1292}, timestamp = {2020-10-27T12:01:58.000+0100}, title = {A High-Speed Trace-Driven Cache Configuration Simulator for Dual-Core Processor L1 Caches.}, url = {http://dblp.uni-trier.de/db/journals/ieicet/ieicet96a.html#TawadaYT13}, volume = {96-A}, year = 2013 }