%0 Conference Paper %1 conf/fpl/ChenZLTYW23 %A Chen, Ruiqi %A Zhang, Haoyang %A Li, Shun %A Tang, Enhao %A Yu, Jun %A Wang, Kun %B FPL %D 2023 %E Mentens, Nele %E Sousa, Leonel %E Trancoso, Pedro %E Papadopoulou, Nikela %E Sourdis, Ioannis %I IEEE %K dblp %P 228-234 %T Graph-OPU: A Highly Integrated FPGA-Based Overlay Processor for Graph Neural Networks. %U http://dblp.uni-trier.de/db/conf/fpl/fpl2023.html#ChenZLTYW23 %@ 979-8-3503-4151-5

@inproceedings{conf/fpl/ChenZLTYW23, added-at = {2024-05-13T00:00:00.000+0200}, author = {Chen, Ruiqi and Zhang, Haoyang and Li, Shun and Tang, Enhao and Yu, Jun and Wang, Kun}, biburl = {https://www.bibsonomy.org/bibtex/22fdea9fab1906dc5983cf532661fb770/dblp}, booktitle = {FPL}, crossref = {conf/fpl/2023}, editor = {Mentens, Nele and Sousa, Leonel and Trancoso, Pedro and Papadopoulou, Nikela and Sourdis, Ioannis}, ee = {https://doi.org/10.1109/FPL60245.2023.00039}, interhash = {c91028b257cec26364ae0d9fcff7404c}, intrahash = {2fdea9fab1906dc5983cf532661fb770}, isbn = {979-8-3503-4151-5}, keywords = {dblp}, pages = {228-234}, publisher = {IEEE}, timestamp = {2024-05-20T07:23:27.000+0200}, title = {Graph-OPU: A Highly Integrated FPGA-Based Overlay Processor for Graph Neural Networks.}, url = {http://dblp.uni-trier.de/db/conf/fpl/fpl2023.html#ChenZLTYW23}, year = 2023 }